What we know

Intel’s EMIB (Embedded Multi-die Interconnect Bridge) and Foveros are advanced chip packaging technologies that enable heterogeneous integration and scaling of chips in multiple dimensions. EMIB, first introduced commercially in 2017, provides high-bandwidth, low-latency connections between chiplets within a single package without requiring a silicon interposer. Foveros, launched in 2019, supports 3D stacking of logic chips, allowing vertical integration of different process nodes and functions. Intel continues to develop both technologies, with roadmaps showing plans for increased adoption and improvements in interconnect density and power efficiency. EMIB was introduced commercially in 2017; Foveros followed in 2019. EMIB enables lateral integration of multiple dies without a silicon interposer. Foveros allows vertical stacking of logic chips across different process nodes. Intel’s roadmap points to expanded use and enhancements of these technologies in future products.

Why it matters

5D) and vertical (3D) integration. This flexibility lets Intel combine different IP blocks, process technologies, and memory types within a single package, improving performance, power efficiency, and design versatility. Intel’s continued investment in these packaging methods signals their importance for upcoming CPUs, GPUs, and accelerators.

What is still unknown

Details on independent performance validation, supported languages, and a broader timeline for widespread adoption remain unclear. No independent tests of accuracy or efficiency have been reported.